Analysis of delay effects and design of output filter for IFOG

WEI Yan

(Shanghai Institute of Spaceflight Control Technology，Shanghai 200233，China)

Analysis of delay effects and design of output filter for IFOG

WEI Yan

(Shanghai Institute of Spaceflight Control Technology，Shanghai 200233，China)

The delay of the digital circuit of an IFOG is inevitable，which will result in the noises in the output data and reduce the accuracy of the IFOG.In order to solve the problem，the effects of the delay of the digital circuits to the nonlinearity of the output of the IFOG are discussed，and the method of improvement in designing the digital circuits is recommended.The design of the output filters for reducing the noise from nonlinearity of D/A is put forward，and some of the attentions are also pointed out when changing the type of the average or using the filters other than an average.The purpose of elimination of the effect of the delay is obtained with the proposed design.The simulation shows that the SD of the noise in the output data due to the delay can be limited to zero.

IFOG;delay;filter;average;nonlinearity

The closed-loop IFOG (Interferometric Fiber-optic Gyroscope) has been developed for many years and it has been put into the application in many fields[1-4].In many cases，an IFOG with high performances is pursued with help of Kalman Filter or Wavelet Filter[5-7].The accuracy and dynamics are both criterion for the application.Duo to the limit of the bits of the D/A in the IFOG，nonlinearity will occur in the output data，which will also result in noises.The delay in the digital circuit will worsen the nonlinearity.The output filter is a very important method to smooth the noise，and is truly an efficient way，if properly designed.

In the reference [8]，the characteristic of D/A was discussed，but the nonlinearity resulted was not researched further.In the reference [9]，the design of the controller and the output filter was discussed，but the effects of the delay were not considered.In this paper，the focus will be on the effects of the delay and the output filter，and the design suitable for the engineering application is also put forward.

1 The modeling of the IFOG

The closed-loop IFOG is made of SLED，PINFET，fiber optic coil，IOC，electronic circuits and etc.The main purpose of the IFOG is to measure the vector of the rotation speed of the carrier refer to the inertial space.It transfers the rotation speed?ininto the Sagnac phaseΦsagby the Sagnac interferometer and outputs the data?outrepresenting the input rotation speed.The circuits detect the difference between the Sagnac phaseΦsagandthe feed-back phaseΦf，and then calculate the output data?outwhich generates the next feed-back phaseΦf.

The main principle outline is shown in Fig.1.

Fig.1 The outline of the IFOG

In Fig.1，?inis the input of the rotation speed;Φsagis the Sagnac phase;Φfis the feed-back phase;Φbis the phase of a square wave bias;ΔΦis the sum of theΦsag，-ΦfandΦb;?sis the phase step of the digital phase ramp;?outis the output of the IFOG;τis the propagation time of the light in the fiber optic coil.

The Sagnac effect is a linear transformation and can be regarded as a proportional coefficientK1.The function of the detector biased by ±π/2，pre-amplifier，sample and demodulator can be simplified by a proportional coefficientK2，assuming that ΔΦis a small quantity.The function of phase modulator and the phase ramp with D/A convertor and zero-order holder is countervailed，thus the feed-back loop can be simplified as a coefficientK3.The simplified model of the IFOG is shown in Fig.2.

Fig.2 The simplified model of the IFOG

Fig.3 The control signal scheme of the IFOG

The main designing work for the digital signal processorD(z) is to design the controllerC(z) and the output filterF(z).Usually，an integrator is adopted as the controller and an average as the output filter，as shown in Fig.3.The transfer function of the digital integrator is，and the average，whereais the coefficient of the integrator，kthe delay of the digital signal andmthe length of the average.The closed-loop transfer function of the phase step?s(z) to the input?in(z) is

The steady output of the phase step?sfor the constant input?inis

Because the digital bits of a D/A convertor available is limited，such asNda，the output data of the integrator withNcbits have to be cutoff byNdabits and discard the excessive bits of the data by right shifting operation of the register to generate the phase step?s，which will result in the nonlinearity of the output data for the small input of the rotation speed[10].

If the constant input?inis precisely equal toK3/K1，there will be no problem for the controller to generate the phase step?sas “1” through the feedback control and have a steady output.If the input?inis precisely equal to half ofK3/K1，the controller has to generate the phase step?sas “1” and “0” periodically in a steady way.If the input?inis precisely equal to 2-nK3/K1，the controller has to generate the phase step?sas one “1” and 2n-1 continuous “0” periodically in a steady way，which will result in nonlinearity in the output data tremendously and the noise as well.The solution to the above problem is to average the phase step?s，which is the basic reason why the output filter uses an average of 2ndata to smooth the periodic phase step?sof one “1” and 2n-1 continuous“0”.That will guarantee the resolution of the closed-loop IFOG usually.

2 The analysis of the effects of the delay

As usual，the effects of the delay of the digital signal are negligible，because the delay time is too short to affect the dynamics of the system.Nevertheless，some of the considerations have to be taken into.

If we need a resolution of quarter ofK3/K1for the closed-loop IFOG，a constant input of quarter ofK3/K1will make the controller to generate the phase step?sas one “1” and three continuous “0” periodically in a steady way，and an average of 4 data is enough for smoothing the noise due to the nonlinearity of the D/A.All these are under the consideration that the delaykis equal to 1.If the delaykis equal to 2，the controller will generate the phase step?sas two continuous “1” and six continuous“0” instead of one “1” and three continuous “0”periodically in a steady way，which need an average of double length to obtain the accurate steady output?out.Fig.4 shows the simulation of the phase step?swith different delayk.That will be a great disaster for the IFOG of the resolution of one thousandth ofK3/K1with the delaykgreater than 2，because the steady period of the phase step?swill be more than 2 thousand data.

Fig.4 The simulation of ?s for the different delay k

In general，the delay of the digital circuit is inevitable.One of the solutions to the problem above is to lengthen the data of the average，which will reduce the dynamic band width of the IFOG.Another way is to improve the designing of the digital circuit to limit the delaykto 1.Using a higher frequent pulse for the working reference is a good idea，such as the pulse for the sample which is much higher than the eigen frequency of the IFOG.

3 The design of the output filter

In the least structure of a closed-loop IFOG，there is no need of the output filter and the phase step?swill be the final output.Certainly，the resolution of the IFOG is limit to that of the D/A，which cannot meet the needs of the engineering application.In order to get higher resolution and reduce the noise duo to the nonlinearity of D/A at the same time，an average of lengthmis adopted as the output filter.The digital transfer function of the output filter is

Usually，the lengthmof the average is about the type of 2n.A filter of 211long is recommended for the IFOG of the resolution of 2-10K3/K1and the delay of 2，the SD (Stand Deviation) of which is about zero.Ifτis equal to 1.5 μs，the band width of the filter above will greater than 100 Hz and the dynamic frequency spectrum of the filter are illustrated in Fig.5.

Fig.5 The frequency spectrum of the output filter

Any changes of higher resolution than 2-10K3/K1and more delay than 2，the length of the filter above cannot cover the steady data period of the phase step?sand the steady output of the filter will result in the noise，which will affect the steady characteristic of the IFOG.

The change of the structure of the average is not recommended，especially the reduction of the length of the average.For example，for the purpose of faster decline speed of the magnitude of the spectrum in the high frequency band，a usual design is to reduce the length of the average and increase the stage of it.For example，instead of an average of 4 data，a filter of two stage of an average with 2 data is designed for an IFOG of the resolution of 2-2K3/K1，where the delaykis equal to 1.The digital transfer function of the filter isF(z)，as follows.

If the input?inis precisely equal to 2-2K3/K1，the filter will not output the steady accurate data of 0.25 with the SD of zero，but the steady data of 0，0.25 and 0.5 in an uncertainty way with the SD of 0.204.The transfer functionF(z) above can be expressed as follows

The function of the filter above is not an average any longer，but a kind of FIR (Finite Impulse Response) filter.Then，we have to be careful to reduce the length of the average or deal with any filter other than an average，such as IIR (Infinite Impulse Response) filters，FIR filters and etc.

4 Conclusion

The delay in the design of a digital circuit is inevitable and will worsen the nonlinearity of the D/A.The best way to overcome the problem is to limit the delaykto less than 2 or select other reference pulse with higher frequency.

In order to obtain a good resolution of the closed-loop IFOG，an average as an output filter has to be adopted to smooth the data of the phase step?s.The length of the average must not less than the period of the data of the phase step?s，otherwise the SD of which will not trend to zero.More attention has to be paid when other kinds of filters are dealt with，which have not any function of the average at all.

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1005-6734(2014)03-0396-04

10.13695/j.cnki.12-1222/o3.2014.03.022

光纖陀螺延遲影響分析及輸出濾波器設計

衛 炎
（上海航天控制技術研究所，上海 200233）

干涉式光纖陀螺的電子線路中不可避免會產生延遲，使得輸出增加噪聲并影響陀螺精度。為了解決上述問題，討論了光纖陀螺數字電路的延遲對輸出的非線性影響，并提出了相應的改善其影響的設計方法。另外對于為了減小數模轉換器非線性噪聲而增加的輸出濾波器，也進行了設計，并同時指出了改變平均算法形式或使用平均算法以外的濾波器時應注意的事項。通過精心設計，可以達到徹底消除延遲影響的目的。仿真結果表明由于延遲引起的輸出噪聲標準差可以限制到零。

光纖陀螺；延遲；濾波器；平均算法；非線性

U666.1

A

2014-02-23；

2014-05-14

衛炎（1960—），男，研究員，從事光纖陀螺研究。E-mail：yanw2008@aliyun.com