基于51核的AES算法高速硬件設計與實現

曾小波,易志中,焦　歆

(1.湖南理工職業技術學院 太陽能工程系,湖南 湘潭　411104;2.上海滕維信息科技有限公司,上海　200072)

基于51核的AES算法高速硬件設計與實現

曾小波1,易志中2,焦歆2

(1.湖南理工職業技術學院 太陽能工程系,湖南 湘潭411104;2.上海滕維信息科技有限公司,上海200072)

摘要為提高算法的效率,降低密鑰運算的復雜度,提升密鑰抵抗強力攻擊和時間攻擊能力,提出一種AES的算法方案。闡述了AES算法原理及片上系統執行AES的工作流程,基于8051軟核AES算法IP原理、設計流程以及硬件模塊的實現方案,并給出了效率分析及在硬件平臺上的驗證結果。仿真結果顯示,用查表法實現AES,其IP核具有高效性,并可為密碼SoC產品的開發體統算法引擎支持。相比較于以往的算法模型,該方案用少量面積換取速度,大幅提高了算法的效率,因此具備良好的應用價值。

關鍵詞對稱加密;AES算法;IP核;片上系統;解密

High-Speed Hardware Design and Implementation of AES Algorithm Based on 51 Core

ZENG Xiaobo1,YI Zhizhong2,JIAO Xin2

(1.Department of Solar Engineering,Hunan Vocational College of Science and Technology,Xiangtan 411104,China;

2.Shanghai Tengwei Information Technology Co.,Ltd.,Shanghai 200072,China)

AbstractAn AES algorithm scheme is proposed for higher algorithm efficiency,lower complexity of key operations and better resistance of the key against brute-force attack and time attack.The AES principles and its on-chip implementation based on 8051 soft-core are presented with workflow system and hardware modules design given.The efficiency analysis and verification results on the hardware platform are provided.Simulation results show that the AES IP core by look-up table method has high efficiency,and offers support for algorithm engine in the SoC decency password product development.A substantial increase in the efficiency of the algorithm is achieved at the mere cost of a small area of the exchange rate compared with conventional algorithms.

Keywordssymmetric encryption;AES algorithm;IP core;system on chip;decryption

AES(Advanced Encryption Standard)是由美國聯邦政府采用的一種區塊對稱加密標準,以此來取代之前的DES,截止至2006年,高級加密標準已成成為最流行的對稱算法[1]。其在軟硬件實現過程中均表現出良好的性能:建立密鑰時間短、靈敏性高、能夠抵抗強力攻擊和時間攻擊[2]。本文利用Ncverilog研究查表法AES算法[3]高速硬件的實現,并采用8051軟核為控制器,將AES作為可移植的IP進行了頂層調試,并給出其相應Verilog模型的仿真結果。本文中所采用的Verilog行為模型為RTL級(Register Transfer Level),是用寄存器這一級別的描述方式來描述電路的數據流方式,即可綜合的。模型接口為標準的Wishbone總線及51接口。……