An electromagnetic simulation assisted small signal modeling method for InP double-heterojunction bipolar transistors

Yanzhe Wang(王彥喆) Wuchang Ding(丁武昌) Yongbo Su(蘇永波) Feng Yang(楊楓)Jianjun Ding(丁建君) Fugui Zhou(周福貴) and Zhi Jin(金智)

1School of Microelectronics,University of Chinese Academy of Sciences,Beijing 100049,China

2High-Frequency High-Voltage Device and Integrated Circuits R&D Center,Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China

Keywords: electromagnetic simulation, InP double-heterojunction bipolar transistor, parameter extraction,small-signal modeling

1. Introduction

Indium-phosphide-based heterojunction bipolar transistors (InP HBTs) have been exploited and investigated for integrated circuits operating during the last decades, with their high power and high-speed characteristics, it is widely used in many technology fields such as optical communications and telephone systems.[1]Compared to silicon-based technologies,InP HBTs have higher electron mobility,better noise performance,and anti-radiation characteristics.[2–4]InP HBTs also have higher thermal conductivity and higher electron mobility than GaAs-based devices, so InP is the most suitable semiconductor material for terahertz applications.[5]

For most high-frequency electronic circuits, transistors are the core active components, they should be characterized and modeled before moving to the circuit design,so transistor modeling plays a fundamental role in its utility.De-embedding is the crucial step in device modeling, it can be conceptually understood as shifting the electrical reference planes closer to the actual DUT,[6]and intrinsic parameters can be extracted accurately only when extrinsic parts (such as probe pads and interconnects)are subtracted from the raw measurement data.De-embedding methods have been developing and improving in recent years,the most widely used open-short method[7]is based on lumped approximation,which is generally applicable within 30 GHz. The four step method[8]addresses issues of substrate coupling and contact effects. An improved three step method[9]was proposed and the method is applied not only toS-parameter measurements but also to large-signal measurements for the first time. The well-known 4-port method[1]treats the parasitic network as a 4-port network, which does not require any equivalent approximation and is compatible with noise de-embedding. The pad-thru-short[3]method accurately removes parasitic parts of the nonshielding input and output interconnects and dangling leg.

As the application frequency of circuit design has reached the terahertz domain and the size of transistor is small enough,the values of extrinsic elements become comparable to values of intrinsic parameters, making it more challenging to de-embed and accurately characterize devices up to the submillimeter wave range.Normally,this is achieved by measurement methods like open-collector (to extract extrinsic resistances and inductances)and cut-off(to extract extrinsic capacitances), these traditional techniques have obvious disadvantages. Open-collector measurement requires a very high base current,which may damage the device and obtain inappropriate data. In addition,the resistances obtained are the mixture of the outer and inner parts. In cut-off measurement,it is difficult to separate the extrinsic capacitance and intrinsic capacitance. Electromagnetic(EM)simulation-based de-embedding is an alternative approach that can solve these problems. Electrical characteristics can be directly obtained from EM simulations if the port and simulation setups are defined properly,the process does not need any standards,and many measurements and errors from measurements can be avoided. Up to now,the method has been applied in the small-signal model building for kinds of transistors such as complementary metal-oxidesemiconductor field-effect transistors,[11,12]GaAs p-type high electron mobility transistors (HEMTs),[13]GaN HEMTs,[14]and InP HBTs.[15–18]Furthermore, the EM simulation approach can also be used in the noise model building for microwave transistors. In Ref.[19],a low-noise transistor model has been developed based on EM simulations.

This paper presents a systematical EM simulation-based method to extract small-signal model for InP DHBTs with three steps. In the first step, the ports for simulations and setups are properly defined. An extended L-2L port calibration[2]is used to eliminate the port discontinuity, and the suitable simulation setups is determined by fitting the simulation results and measurements data of OPEN and SHORT structures, this step is illustrated in Section 2. In the second step, the parasitic elements of the device are de-embedded,seven 3D dummy structures are applied to extract parasitic parameters of probe pads, interconnection lines, and electrode fingers,all the dummy structures are simulated in EM simulation software and the simulation results are analyzed in Agilent advanced design system(ADS),this step is illustrated in Section 3.The last step is to extract intrinsic parameters,an intrinsic small-signal model simpler than conventional model[21,22]is proposed, the base-collector resistanceRμand the output resistanceRceare deleted for their relatively high value,Cceis introduced to characterize the capacitance generated from the collector finger and emitter ground bar,this step is illustrated in Section 4. In Section 5, experimental validations for the three transistors with different emitter sizes are performed at four bias points.

2. EM simulation setups and port calibration

The core procedure of this work is electromagnetic field simulation,simulation accuracy directly evolves with the success of the final modeling result, so the simulation settings should be the primary concern and ought to be set up properly to ensure the correctness of the simulation. There are three key aspects to note: Firstly, a radiation boundary should be applied to the airbox of the simulation structures because radiation boundary creates an approximation of free space that allows electromagnetic waves to radiate infinitely far into space.Secondly, lumped ports ought to be applied internally in the solution space. Analogous to a probe of a testing system,the lumped port inputs current signals into the structure, so we must set its port impedance to 50 Ω in order to make it consistent with the internal characteristic impedance of the test system. Thirdly,the lumped port must be calibrated. The excitation scheme in this work mainly refers to the surrounding ground ring approach reported in Ref.[2],the vertical 2D rectangle lumped port touches the simulation structure and the opposite side edge touches the vertical perfect electric conductor bridge, a perfect electric conductor (PEC) is an idealized material exhibiting infinite electrical conductivity or zero resistivity. Hence the parasitism of this excitation mainly comes from PEC bridges and the lumped ports.A lumped port generatesS,Y,Zparameters and fields in EM simulations,therefore its parasitic elements should be de-embedded. We use the extended L-2L method to calculate the parasitic inductance from the PEC bridge and the parasitic capacitance from the port.After port calibration, the two extracted parasitic values are estimated to be a 14 pH inductance and a 4.5 fF capacitance,which are almost independent of frequency as shown in Fig.1,indicating that the calibration technique is reliable. The two parasitic parameters will be subtracted from all the subsequent EM simulation data. All the conditions of simulation structures should be set as close as possible to the actual on-wafer measure conditions. The structure simulated consists of three layers. The top metal is set as gold material with conductivity 3.8×107S/m and a thickness of 0.5 μm. The layer below is BCB,its relative permittivity is set as 2.6,and thickness is set as 7 μm. The two materials above are laid on the InP substrate with a thickness of 600 μm and relative permittivity of 10.6.

Experimental data within 0.1–50 GHz of conventional SHORT and OPEN structures are used as references for checking the correctness of the excitation scheme and simulation settings. Figure 2 shows that EM simulation results of OPEN and SHORT structures fit well with their measurement data,which explains that the simulation settings are reasonable.The determined setups from this procedure will be applied to the subsequent EM simulations.

3. EM simulation assisted extraction of parasitic parameters

The complete small-signal equivalent circuit of InP DHBTs is shown in Fig. 3. Before we start establishing the small-signal model of the intrinsic part,all the parasitic out of the intrinsic part should be de-embedded. The outermost parasitic capacitances (Cpbg,Cpcg,Cpbcg), resistances (Rbx,Rcx,Rex)and inductances(Lbx,Lcx,Lex)are from probe pads,and the similar RCL network of the inner part (Cpbg,Cpcg,Cpbcg,Rbx,Rcx,Rex,Lbx,Lcx,Lex) are the parasitic elements of the electrode fingers.

TheZparameter of the inner electrodes RL network is calculated by subtracting pad parasitic elements and electrode parasitic capacitances from the full-short structure shown in Fig.4(d).

Fig. 4. View of the InP HBT structure in Ansys HFSS. All sizes and layouts are strictly drawn in accordance with the actual device.

Then we can obtain theZparameters of the intrinsic device with Eq.(5),whereYrawis the unprocessed measured data,andZdeemis the impedance parameter to extract intrinsic parameters in Section 4.

As for the rest three structures in Fig.6,i.e.,short-base,short collector and short emitter, they are introduced for considering the influence of mutual inductance between the electrode fingers. As shown in Fig.7,after taking the influence of mutual inductance into account, there exist mutual inductancesMbc,MbeandMceamongLb,LcandLe. TheZparameters of the RL network circled with read dotted line in the full-short structure in Fig.7 should be

Lb,LcandLethat can be calculated with the following equations:

Now that values ofLb,LcandLehave already been solved,we can extractMbc,MbeandMceeasily. Figure 8 gives the extraction results (0.8×10 μm transistor). The electrode inductances with consideration of mutual inductanceLbm,Lcm,Lemcan be calculated by

All the extracted extrinsic parameters are listed in Table 1,and emitter electrode resistance and inductance versus emitter length are shown in Fig.9,the inductance and resistance of the electrode increase as the length of the electrode increases,which proves the physical soundness and consistency of this de-embedding method.

Elements 0.8×7 μm 0.8×10 μm 0.8×15 μm Elements 0.8×7 μm 0.8×10 μm 0.8×15 μm Cpbcg (fF) 1.868 1.814 2.208 Cpbc (fF) 1.972 2.108 2.030 Cpbg (fF) 14.55 14.60 20.65 Cpbe (fF) 8.347 9.739 9.975 Cpcg (fF) 14.49 14.53 20.61 Cpce (fF) 9.224 10.264 10.531 Lbx (pH) 41.55 40.50 40.86 Lbm (pH) 2.289 2.749 4.339 Lcx (pH) 39.75 40.19 40.34 Lcm (pH) 1.363 1.619 2.581 Lex (pH) 8.726 8.178 7.543 Lem (pH) 0.664 0.727 1.181 Rbx (Ω) 0.461 0.464 0.472 Rb (Ω) 2.003 2.669 3.777 Rcx (Ω) 0.449 0.459 0.468 Rc (Ω) 0.306 0.500 0.607 Rex (Ω) 0.160 0.130 0.103 Re (Ω) 0.007 0.009 0.034

4. Extraction of intrinsic parameters

The intrinsic equivalent circuit we proposed is shown in Fig. 10.Rbiis the intrinsic base resistances,Rπis the intrinsic base-emitter resistance.CμandCπare the intrinsic base-collector and base-emitter capacitance,respectively,andCcxis the extrinsic base-collector capacitance.Gm0is the DC transconductance andGmis the small signal transconductance,τis delay time.

Considering the simplicity of the model,we omitted basecollector resistanceRμand the output resistanceRce,because these two parameters have relatively high values. CapacitanceCceis introduced for the characterization of the capacitive parasitic caused by the collector electrode finger and the emitter ground bar,as shown in Fig.12.

First, we use theT–πtransformation[23,24]displayed in Fig. 11 for this equivalent circuit. The three impedance parameters in Fig.11 are

TheYparameters of the intrinsic part can be expressed as

Parameterτis obtained by fitting the measuredSparameters. Table 2 shows the intrinsic parameter extraction results of bias atVce=1.2 V,Ib=60 μA,Vce=1.7 V,Ib=40 μA,Vce=2.2 V,Ib=140 μA,Vce=2.7 V,Ib=160 μA. By this step,all the parameters in the small signal model of the three transistors are extracted.

Vc=1.2 V,Ib=60 μA Vc=1.7 V,Ib=40 μA Elements 0.8×7 μm 0.8×10 μm 0.8×15 μm 0.8×7 μm 0.8×10 μm 0.8×15 μm Ccx (fF) 7.258 8.477 9.205 6.549 11.32 5.299 Cμ (fF) 4.417 4.862 12.32 8.363 5.15 15.05 Cπ (fF) 65.85 60.99 85.95 64.44 46.74 89.31 Cce (fF) 26.93 23.25 24.01 23.25 17.22 24.54 Rπ (Ω) 950 1003 1163 1300 1360 1127 Rbi (Ω) 14.29 13.62 7.860 15.15 16.74 6.908 Gm0 (S) 0.051 0.043 0.030 0.033 0.027 0.030 τ (ps) 0.949 0.918 1.161 1.163 1.02 1.260 Vc=2.2 V,Ib=140 μA Vc=2.2 V,Ib=160 μA Elements 0.8×7 μm 0.8×10 μm 0.8×15 μm 0.8×7 μm 0.8×10 μm 0.8×15 μm Ccx (fF) 8.679 11.22 10.32 5.996 12.89 9.353 Cμ (fF) 6.330 2.507 8.80 7.272 4.554 9.189 Cπ (fF) 122.5 117.5 170.25 92.70 133.3 195.69 Cce (fF) 21.37 26.94 17.38 23.25 26.35 15.04 Rπ (Ω) 545 508.9 452.2 500 421.38 342.06 Rbi (Ω) 13.69 14.73 6.01 12.63 15.06 5.113 Gm0 (S) 0.112 0.096 0.108 0.120 0.124 0.139 τ (ps) 1.418 1.001 1.314 1.02 1.205 1.50

5. Verification and discussion

In order to verify the correctness of the proposed smallsignal model building method, InGaAs/InP DHBT devices with the emitter sizes 0.8×7 μm,0.8×10 μm and 0.8×15 μm are used here for validation. The devices are manufactured in the Microwave Integrated Circuit Research Laboratory of the IMECAS.Measurements were performed at Agilent E8363B vector network analyzer(0.1–50 GHz)after an on-wafer shortopen-load-through(SOLT)calibration.[25]Cascade probe station is used.

Fig.12. Introduced capacitance Cce (circled with red dotted square).

Bias point Vce=1.2 V Vce=1.7 V Vce=2.2 V Vce=2.7 V Ib=60 μA Ib=40 μA Ib=140 μA Ib=160 μA Residual error 1.88% 2.36% 1.55% 1.26%

6. Conclusion

This paper presents an EM simulation-based small-signal model building method for InGaAs/InP DHBTs. Seven dummy structures are simulated to extract the parasitic elements rigorously,and port calibration is performed before simulation. Two typical structures OPEN and SHORT are used to determine the proper EM simulation settings. A simpler intrinsic equivalent circuit is proposed,Cceis introduced to the conventional intrinsic small signal model to characterize the parasitic capacitance generated from collector electrode finger and emitter ground bar,all the intrinsic parameters are obtained through mathematical method carefully.The simulation results of the small-signal model are compared to the measurement data of three kinds of InP HBT devices with different emitter sizes, within the frequency range 0.1–50 GHz, excellent agreements are achieved at four different biases, which proves the effectiveness of the method. The errors ofSparameters are also given. This accurate EM-based simulation method makes it convenient to extract parameters directly,and the method avoids several disadvantages of conventional methods,leading to a more reliable small-signal building technique.